Students are initially taught issues concerning the principles and practices of sequential logic. Emphasis is placed on topics that are not covered in the course of Logical Design such as a) timing analysis of digital systems, studying instability and how it is treated with the use of synchronizers, b) numerical systems of fixed and mobile subsystems, and c) spatial and time parallelism for increasing the performance of a digital system.
Students are then taught the VHDL material description language for simulation and proper composition through the data path circuits and the control unit of an ARM architecture processor and the required testbenches. First, a description of simple combination and sequential circuits is given (e.g. decoders, multiplexers, registers, meters), then the description of arithmetic circuits (adders, subtractors, comparators, ALU unit, sliders and rotators), and the control unit as a machine of finite states (for multi-cycle microarchitectures), and finally the description of memory devices (ROM, RAM and registry files).
Finally, students are taught the architecture of the ARM processor (commands, symbolic language, programming, machine language) and learns the details of the actual design of an ARM architecture processor for all three basic microarchitectures (one cycle), one cycle, many cycles and which adopt different compromises between performance and cost. The compromises are analyzed in depth, so that the student understands the usefulness of the basic micro-architectures in practice.
In the workshop, students use the software tools of XILINX (WebPACK edition of Vivado Design Suite) to design, verify the correct design with simulation (writing the necessary testbenches), to compose and implement, first, measuring meters and machines situations, then a UART asynchronous serial communication unit and finally an ARM architecture processor core.
Optionally, instead of a written exam, students expand their knowledge by implementing the core ARM architecture processor and UART module on Xilinx's Zedboard development card, which hosts an FPGA of the Xyninx processor's Zynq 7000 series between communication and installation, the computer (host PC) and the verification of the correct design at the FPGA (FPGA in-the-loop verification) level.
The course covers the following topics:
• Summary in matters of principles and practices of sequential logic.
• Digital system timing analysis, metastasis and synchronizers.
• Numerical systems of fixed and mobile subdivisions.
• Increasing digital system performance with spatial and temporal parallelism.
• VHDL material description language for simulation and synthesis.
• Description of digital building blocks in VHDL.
• ARM processor architecture (commands, symbolic language, programming, machine language).
• Detailed design of ARM architecture processor for all three basic microarchitectures (one cycle, multiple cycles and channeling).
• Performance analysis and cost for the three basic microarchitectures.
• Use of Zedboard development card and verify the correct design at FPGA level.
- At the beginning of the course, students receive in electronic form all the slides of the lessons organized in such a way that they are initiated not only in the logical design, but also in the learning process and in the development of reasoning. Lecture slides are used by the students during the lectures as a "notebook" in which they can mark any questions or clarifications as well as the solutions of selected exercises. At the end of the lectures, students who attended the course, will own a complete packet of educational material, created with their own participation. This material will form the basis of their preparation for the final evaluation.
- Laboratory booklet.
- The course is based on the book "Digital Design and Computer Architecture, ARM Edition", by Sarah L. Harris and David Money Harris, (scientific editing in Greek: A. Paschalis), Kleidarithmos, 2019. (original title: "Digital Design and Computer Architecture, ARM Edition ”, Elsevier / Morgan Kaufmann, 2016).