Logic Design Lab

Semester:
1ο
Course Type:
Optional Laboratory courses (EP)
Track:
-
Code:
K02ε
ECTS:
2
TEACHING HOURS per week
Theory:
-
Seminar:
-
Laboratory:
2
Specializations
Foundations of Computer Science (Ε1):
-
Data and Knowledge Management (Ε2):
-
Software (Ε3):
-
Hardware and Architecture (Ε4):
-
Communications and Networking (Ε5):
-
Signal and Information Processing (Ε6):
-
Related Courses
Detailed Description
Course Content

This course is about digital circuits design and implementation using Field Programmable Gate Arrays (FPGAs) technologies using CAD tools from Xilinx (Vivado Design Suite WebPACK edition).
In details, the course is about digital circuits design using the VHDL hardware description language, under specific timing and I/O constraints, synthesis, implementation and bitstream generation targeting specific FPGA target technology, as well as, verification at all levels of development (VHDL source code, post synthesis, post place & route) using simulation, debug and FPGA validation using a proper FPGA development board.
The digital circuits to be designed and implemented are of similar academic importance and complexity to those taught in the undergraduate course of Logic Design (K02).
The development board that will be used in the training process is the Xilinx Zedboard hosting a Xilinx Zynq 7000 series FPGA.


The course includes the following sections:
1. Digital system implementation technologies - Introduction to Xilinx FPGA technology
2. Methodology and FPGA development flow
3. Downloading, licensing and installation of Xilinx FPGA development tools. Introduction to development board (Zedboard)
4. Basic concepts of modeling with VHDL
5. Basic verification using VHDL testbenches
6. Basic combinational circuits (decoders, encoders, multiplexers, etc.) with VHDL
7. Basic arithmetic operations (addition, subtractions, comparisons, multiplications, etc.) with VHDL
8. Basic state elements (latches, flip-flops, registers, shift registers) with VHDL
9. Counters with VHDL
10. Memories with VHDL
11. Finite State Machines with VHDL
12. Timing constraints and design for timing closure
13. Design using Xilinx IP cores

LITERATURE AND STUDY MATERIALS - READING LIST

1) Digital Design (VHDL): An Embedded Systems Approach Using VHDL, Peter J. Ashenden, (In Greek by M.Psarakis, N. Kranitis and D. Gizopoulos), 1st Edition, 2010, New Technologies Publications
2) Circuit Design with VHDL, V.A. Pedroni, 1st Edition, 2008, Kleidarithmos Publications