ISA of RISC architectures (review)
Basics of pipelining,
Pipelining in MIPS microprocessors.
Datapath and control unit design for pipelined CPU.
Data, control and structural hazards.
Superscalar and out-of-order basics.
Cache memories concept.
Caches architectures and algorithms.
Storage devices performance and reliability.
Microprocessor systems interfacing.
“Computer Organization and Design: the Hardware/Software Interface”, 4th Edition, D.A.Patterson, J.L.Hennessy, Elsevier/Morgan Kaufmann, 2010.