Course ContentISA of RISC architectures (review)
Basics of pipelining,
Pipelining in MIPS microprocessors.
Datapath and control unit design for pipelined CPU.
Data, control and structural hazards.
Superscalar and out-of-order basics.
Branch prediction.
Cache memories concept.
Caches architectures and algorithms.
Virtual memory.
Input/output devices.
Storage devices performance and reliability.
Microprocessor systems interfacing.